介绍了基于Actel反熔丝FPGA的嫦娥一号卫星干涉成像光谱仪时序控制模块设计.概述了时序控制模块的功能要求，详细描述了时序控制模块外部时序接口和内部时序接口，给出了时序控制模块设计的参量配置、逻辑结构和简要结果.各项地面试验和一年的在轨飞行结果表明该设计合理可靠.

Some information about the timing and control module design based on Actel’s antifuse FPGA of the Interference Imaging Spectrometer (IIS) of Chang′e-1 Satellite was given.Functional requirements was introduced.The external timing interface and internal timing interface were discribed in detail.And,the parameter configuration,logical structure and some results were treated.Various on-ground tests and one-year on-orbit operation show that the design is reseanable and reliable.