针对制作尺度<10 μm的超小微细阵列网板非常困难的问题，提出了采用过电铸工艺制造超小尺寸微细阵列网板的方法。建立了过电铸工艺过程的电场模型，利用有限元分析技术对过电铸工艺过程进行模拟仿真。选取优化的工艺参数(烘胶 120 ℃/60 min，曝光 3 000 mJ/cm2，显影 2 min等)利用光刻制作了高度为50 μm、直径为50 μm的AZ EXP 125nXT-10A光刻胶群柱结构，以此胶膜结构作为模具进行了过电铸工艺实验，并与仿真结果进行对比，结果证明了有限元仿真的正确性。最后，通过过电铸缩孔2 h获得了厚度达70 μm，孔径为4 μm的微细阵列网板结构。实验表明，过电铸工艺是一种低廉、安全、可批量生产的制作超小阵列网板的方法。

The over-plating technology was introduced to fabricate micro hole arrays, for it is difficult to fabricate a micro hole array with the size less than 10 μm by traditional methods. A mathematical model was presented to simulate the over-plating process by Finite Element Method (FEM). Using the optimized parameters (bake 120 ℃/60 min, exposure 3 000 mJ/cm2, and development 2 min),the AZ EXP 125nXT-10A resist structure in a diameter of 50 μm and a height of 50 μm was prepared, and then the over-plating technology was employed to shrink the micro hole. The experimental result shows that the simulation result is correct. Finally,a micro hole array in a diameter of 4 μm and a height of 70 μm was fabricated after over-plating 2 h. The result indicates that over-plating is a simple and low cost method to fabricate micro hole array, and it is suitable for batch production.