搭建了一个合理的试验平台，利用FPGA产生10 bit数字自校图形，经过LVDS同步串口传输，在数据接收端处理串转并数据送入图像采集卡，通过实时观察接收图形是否正常来判断该传输速率下的可靠性。分别研究了基于FPGA片内低压差分模块和专业差分转换芯片的两种应用方案。通过大量试验得出结论：两种方案的最高传输速率，前者约能达到152 Mbit/s，后者约为125.2 Mbit/s。考虑到工程实际中可能面临的各种复杂应用环境，推荐适当降额应用。

This paper tries to exam the transmission bandwidth by establishing a scientific test-platform. The paper provides a test pattern formed by 10 bit raw image data which is generated by FPGA as transmitter. The receiver performs data conversion serial-to-parallel and then sends image data as well as clock and enable signals to the image grabber. The transmission reliability is estimated by checking the real-time received test pattern through the 3-wire LVDS serial port. From abundant experiments, the paper gets two results: when LVDS is implemented by imbedding modules in FPGA, transmission bandwidth is approx 152 Mbit/s; when LVDS is implemented by special LVDS devices, transmission bandwidth is approx 125.2 Mbit/s. In practical application cases, bandwidth derating is advised.