液晶与显示, 2013, 28 (2): 284, 网络出版: 2013-04-15   

多路高速短消隐期线阵CCD图像数据存储设计

Design of Multi-Channel High-Speed and Short Blanking Period Linear CCD Image Data Storage
作者单位
中国科学院 长春光学精密机械与物理研究所, 吉林 长春 130033
摘要
针对频率超过100 MHz的高速航空航天遥感相机图像数据瞬时并行存储困难问题, 提出了一种多路高速短消隐期CCD图像数据存储的方法。先将各路图像数据并行存储到SDRAM阵列, 然后再逐路读出图像数据并经采集卡存储到主机的硬盘上; 针对SDRAM需定时刷新开销大的问题, 将输入图像数据进行位宽变换, 降低SDRAM的读写时钟频率; 采用串并转换和并串转换操作结合异步FIFO进行不同时钟域数据接口, 解决了高速下图像数据非整数倍位宽转换难题, 并给出了SDRAM最低的工作频率和异步FIFO的最小深度的计算公式。研究应用结果表明, 以FPGA为数据处理和控制核心的设计满足应用要求, 并行接收总数据率高达4.13 Gbit/s。
Abstract
In order to solve the problem that the image data for the remote sensing aerospace camera is hard to store parallelly,which frequency is over 100 MHz, a multi-channel high-speed short blanking period CCD image data storage method is put forward. Firstly multi-channel image data are parallelly stored to SDRAM array, and then read out image data from SDRAM array and finally stored to computer′s hard disk channel by channel via the frame grabber; for the problem of SDRAM fixed time refresh,the input image data′s width is changed in order to reduce the SDRAM clock frequency; serial-parallel conversion and parallel-serial conversion operation combined with asynchronous FIFO are used as interface of diffe-rent clock domains,in order to solve the high speed image data non-integer times of the data width conversion, the formulas which are minimum depth of asynchronous FIFO and lowest operating frequency of the SDRAM are given. Research and application results show that the design based on FPGA as the data processing and controlling center meets the application requirements,the total parallelly writing data rate is up to 4.13 Gbit/s.

余达, 龙科慧, 徐东, 赵莹, 王冶, 陈佳豫, 刘金国. 多路高速短消隐期线阵CCD图像数据存储设计[J]. 液晶与显示, 2013, 28(2): 284. YU Da, LONG Ke-hui, XU Dong, ZHAO Ying, WANG Ye, CHEN Jia-yu, LIU Jin-guo. Design of Multi-Channel High-Speed and Short Blanking Period Linear CCD Image Data Storage[J]. Chinese Journal of Liquid Crystals and Displays, 2013, 28(2): 284.

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