功率器件的热阻是预测器件结温和可靠性的重要热参数, 其中芯片粘接工艺过程引起的粘结层空洞对于器件热性能有很大的影响。采用有限元软件Ansys Workbench对TO3P封装形式的功率器件进行建模与热仿真, 精确构建了不同类型空洞的粘结层模型, 包括不同空洞率的单个大空洞和离散分布小空洞、不同深度分布的浅层空洞和沿着对角线分布的大空洞。结果表明, 单个大空洞对器件结温和热阻升高的影响远大于相同空洞率的离散小空洞; 贯穿粘结层的空洞和分布在芯片与粘结层之间的浅空洞会显著引起热阻上升; 分布在粘结层边缘的大空洞比中心和其他位置的大空洞对热阻升高贡献更大。

Thermal resistance is a key parameter to estimate the junction temperature and reliability of the power device. The solder layer voids inevitably left by the die attach process have much effects on the thermal performance of the device. In this study, finite element analysis (FEA) by Ansys Workbench was carried out to precisely model the solder layer with various voids configurations in TO3P package. The results show that for equivalent voiding percentage, thermal resistance increases more for large coalesced void in comparison to the small distributed voids. In addition, the voids extending through the entire thickness of solder layer and voids formed between the chip and solder layer can significantly increase the thermal resistance and junction temperature. Large voids at the edge of solder layer contribute more rise of thermal resistance than that distributed on the other area of the layer.