为了吸收光传输网中由于源和目的时钟来自不同的时钟源而产生的频偏，采用异步映射方式，设计了一种基于同步时钟产生均匀时钟缺口的ODU0映射到ODU1的电路。映射中通过异步FIFO（先入先出）产生均匀的时钟缺口，并通过此时钟处理客户数据，完成客户数据的时隙间插。仿真和FPGA（可编程门阵列）测试结果表明，该电路能够实时、准确地完成传统映射中ODU0到ODU1的映射；与传统映射电路相比，该电路大大减少了锁相环的使用，使电路简单经济。

In order to absorb the frequency offset generated due to source and destination clocks from different sources in Optical Transport Networks (OTN), a circuit is designed by asynchronous mapping, in which sync clockbased ODU0 that generates uniform clock gaps is mapped to ODU1 and the clock gaps are generated in the mapping by asynchronous FIFO. The client data is processed by this clock and mapped into appropriate time slots. Simulation and FPGA test results indicate that this circuit can complete the traditional mapping from ODU0 to ODU1 in realtime and accurately. Compared with the traditional circuits, it greatly decreases the usage of PLL and makes the circuit more economical.