电光与控制, 2014, 21 (5): 92, 网络出版: 2014-05-22
模拟集成电路的边界扫描可测性设计方案
A Built-in-Test Scheme for Analog Integrated Circuit Based on Boundary Scan Technology
模拟集成电路 可测性设计 功能测试 analog integrated circuit testability design function test IEEE 1149.4 IEEE 1149.4 FPGA FPGA
摘要
提出了一种基于边界扫描技术的模拟集成电路内建自测试方案。该方案依照IEEE 1149.4边界扫描测试标准, 在添加极少电路元件的基础上, 增加了电路性能测试单元(FTM), 能够充分利用电路系统中已有数模混合资源, 通过控制器内部向被测电路施加激励, 完成模拟集成电路的功能性测试。采用Cyclone II系列芯片EP2C35F672C8实现测试系统设计, 并以模拟集成滤波芯片MAX292为被测核心电路展开实验, 其频率特性的测试结果表明了该测试方案的正确性和系统测试的有效性。
Abstract
A built-in-test scheme was proposed based on boundary scan technology for analog integrated circuit.Based on IEEE 1149.4 standard and with few added circuit elementsa function test module (FTM) was designed to complete the functional test by making full use of the existing mixed-signal circuit system resources and stimulating the circuit-under-test.A boundary scan testing system based on FPGA was designed by using the analog integrated chip MAX292.The frequency characteristic test result proved the correctness of the test scheme and the effectiveness of the system test.
薛冰, 冯长江, 王聪丽, 张泽建. 模拟集成电路的边界扫描可测性设计方案[J]. 电光与控制, 2014, 21(5): 92. XUE Bing, FENG Chang-jiang, WANG Cong-li, ZHANG Ze-jian. A Built-in-Test Scheme for Analog Integrated Circuit Based on Boundary Scan Technology[J]. Electronics Optics & Control, 2014, 21(5): 92.
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