为了评估光收发模块I2C通信的鲁棒性, 设计了I2C总线极限测试控制器。根据I2C通信协议, 设计超出极限一定范围的参数, 在CPLD(复杂可编程逻辑器件)上通过Verilog HDL设计该控制器, 主要实现频率测试和线路特性测试两大类功能, 通过软件仿真和硬件实现验证了设计的正确性。该控制器也可以实现对其他种类I2C从器件的测试, 只需更改设备地址、偏移地址等相关参数即可。

This paper designs an I2C bus limit test controller for assessing the robustness of the I2C bus communication of optical transceiver modules. In this design, the parameters exceed the limits by a certain range according to the I2C communication protocol. This controller is designed on CPLD using Verilog HDL, which is used to perform two main functions, I2C frequency test and bus line characteristics test. Software simulation and hardware implementation verify the correctness of this design. This controller can also conduct tests of other kinds of I2C slave devices with the only need to change device address, offset address and other relevant parameters.