研究了过孔接触电阻变化规律,并进行机理分析,为优化薄膜晶体管的过孔设计提供依据.首先,运用开尔文四线检测法对不同大小、形状、数量的钼/铝/钼结构的栅极和源/漏层金属与氧化铟锡连接过孔的接触电阻进行测试.然后,通过扫描电子显微镜、能量色散X射线光谱仪和聚焦离子束显微镜对过孔内部形貌进行表征.最后,对过孔接触电阻变化规律进行机理分析.实验结果表明:过孔面积越大,接触电阻越小;过孔面积相同时,长方形过孔的接触电阻小于正方形过孔的接触电阻,多小孔的接触电阻小于单大孔的接触电阻,栅极金属与氧化铟锡的过孔接触电阻小于源/漏层金属与氧化铟锡的过孔接触电阻.为了降低钼/铝/钼与氧化铟锡连接过孔的接触电阻,过孔面积尽可能最大化,采用长方形过孔优于正方形过孔,多小过孔优于单大孔设计,同时优化过孔刻蚀工艺,减少过孔内顶层钼的损失.

In order to optimize via hole design of TFT array substrate and reduce via hole contact resistance,the contact resistance of different size,shape,number of Mo/Al/Mo and Indium-Tin Oxide (ITO) connection via holes are tested by Kelvin Four-terminal sensing.Then via hole morphology is characterized by scanning electron microscopy (SEM),focused ion beam (FIB) and energy dispersive spectroscopy (EDS).Finally,the mechanism of via hole contact resistance test results are analyzed.Experimental results indicate that the bigger via hole area is,the smaller the contact resistance will be,and in the same via hole area,the contact resistance of rectangular via hole is smaller than that of a square via hole,the contact resistance of the multi small holes is smaller than that of the single big via hole,the via hole contact resistance of Gate metal and ITO is smaller than that of SD metal and ITO.For reducing via hole contact resistance,via hole area is maximized.The rectangular via hole is better than that of the square via hole,the multi small holes are better than that of the single big via hole,and via etch process is optimized to reduce top Mo loss.