为了使计算系统具有低功耗和容错能力,基于可逆逻辑设计了一种容错的通用移位寄存器。 提出了一种新型的容错可逆逻辑门(Parity-preserving D flip- flop gate, PP- DFG), 利用它和存在的 容错门,完成了寄存器和多路数据选择器的设计。综合上述模块,构建了容错可逆的通用移位寄存器 电路,用Verilog 硬件描述语言建模,仿真显示电路逻辑结构正确。同现有电路相比,根据量子代价、 延迟和无用输出对其进行性能评估,结果表明该电路不仅具有容错功能,而且性能提高了16%～48%。 设计的电路可作为一种重要的存储元件应用于未来的低功耗计算系统。

In order to make the computing system with low power consumption and fault-tolerant ability, a fault-tolerant universal shift register was designed using reversible logic. A new reversible fault-tolerant gate named Parity preserving D flip- flop gate (PP- DFG) was proposed. Some circuits such as register and multiplexer were designed using PP- DFG and existing gates. Based on the above modules, the fault-tolerant reversible universal shift register was built. It was modeled in Verilog hardware description language for verification. Simulation results indicate that its logic structure is correct. Compared with the existing ones in terms of quantum cost, delay and garbage outputs, the proposed circuit not only supports fault-tolerant but also has 16%～48% performance improvement. This circuit can be used as an important storage element applied in future low-power computing system.