脉冲数字成型滤波器属于有限冲激响应(FIR)滤波器的一种，常规做法是通过传统的乘累加(MACs)方法来实现，即通过对输入信号与单位冲激响应进行线性卷积。但是，随着成型滤波器系数的增加，这种卷积运算势必会占用大量的MAC 单元以及延迟单元，导致现场可编程门阵列(FPGA)硬件资源紧张，系统延迟增大，设备成本增加。本文联合了FIR 成型滤波器群延时特征以及基带数字调制符号特性，提出了一种新的查找表(LUT)结构的FIR 滤波方法，并且在FPGA上实现。软硬件仿真结果表明，这一方法无论从精确度和资源利用上都具有一定的优势。

As a kind of Finite Impulse Response(FIR) filters, pulse shaping FIR filter is implemented by Multiply-Accumulates(MACs), which performs convolution between input signal and unit pulse respond. Nevertheless, the convolution will cost a lot of MACs as the coefficient of filters increases. This will cause the shortage of Field Programmable Gate Array(FPGA) MACs, increase the system delay and device cost. According to group delay of pulse shaping FIR filter and base band modulated symbol character, a new implementation method for Pulse Shaping FIR filters based on Look-Up-Table(LUT) of FPGA is proposed. The results of software and hardware simulation demonstrate the method is area-efficient without any accuracy loss.