模拟数字转换器(ADC)是智能化传感器的一个重要组成部分。阵列型传感器应用对 ADC的功耗及芯片面积都具有较高的要求, 同时传感器本身特性要求 ADC具有较高的精度, 对阵列型传感器用 ADC的设计提出了挑战。在分析各类型 ADC的性能优劣势的基础上, 提出了应用增量型 Sigma-Delta ADC来设计阵列型传感器应用。介绍了增量型 Sigma-Delta ADC的架构设计以及电路设计, 并在 0.18.m CMOS工艺下流片。在 40 kS/s的转换速度下, 所设计的 ADC达到了 15 bit的精度, 功耗为 58.W, 单个 ADC的芯片面积为 10.m×530.m。测试结果表明增量型 Sigma-Delta ADC非常适合于阵列型传感器应用。

The analog-to-digital converter (ADC) plays an important role in array sensor applications. This kind of applications imposes very stringent power and chip area restriction to the ADC. On the other hand, the sensor itself requires high-resolution of the ADC. All these requirements place challenge to the ADC design. By carefully study of the ADC topology, the incremental Sigma-Delta ADC is proposed as it produces better resolution, power and chip area trade-off. The topology and the circuit design of the proposed incremental Sigma-Delta ADC are introduced in details. Implemented in a 0.18.m CMOS technology, the proposed ADC consumes 58.W power consumption at the conversion speed of 40 kS/s and produces 15 bit digital output. The chip area of one single ADC is 10.m×530.m. The measurement result proves the proposed incremental Sigma-Delta ADC is suitable for array sensor applications.