设计实现了一种超高速数据采集系统。通过在FPGA(现场可编程门阵列上)采用8个不同相位的时钟进行移相合成采集, 采用一颗125MSPS采样率的ADC芯片成功实现了1GSPS采样率的高速采样。同时通过对采样数据进行累加求平均的滤波运算, 有效地消除了背景噪声, 提高了采样的精度。为了实现大数据量的采集, 采用了DDR2作为存储器, 其具有容量大, 速度快, 成本低的特点。FPGA采用Xilinx的Spartan6系列, 内置了DDR2接口控制器, 大大简化了设计。设计的高速数据采集系统在ISE软件中进行了综合, 并在FPGA板上进行了实测, 性能良好, 实现了系统需求的各个指标。

An ultra high speed data acquisition system design and implementation based on FPGA(Field Programmable Gate Array) is introduced. A novel shift phase clock acquisition and synthesis method is used. 1GSPS data acquisition is achieved with a single 125MSPS ADC chip. The average filter is used to reduce the noise on the acquisition signal and the precision is improved. The design is implemented in a Xilinx Spartan 6 series FPGA and with DDR2 memory as the data storage. Good result is demonstrated.