通过锁相环电路(PLL)，不仅将外部系统提供的具有高频率准确度但相位噪声较差的主时钟信号转化为高频率准确度、低相位噪声的内部时钟信号，同时也满足了内外部系统的相参要求。通过仿真和测试，重点分析了锁相环电路中环路滤波器的环路带宽对输出信号相位噪声的影响。测试结果显示，当环路带宽为100 Hz 时，锁相环的输出信号在偏离载波1 kHz 处的相位噪声与其内部振荡器在此处的相位噪声基本一致；而当环路带宽为500 Hz 时，输出信号在偏离载波1 kHz 处的相位噪声会由于环路影响，相比内部振荡器产生8 dB 左右的恶化。设计所得时钟源在输出100 MHz 信号时，其相位噪声优于-147 dBc/Hz@1 kHz，相比外部参考时钟信号改善了12 dB,并且其频率准确度可达1×10^-9。

By the circuit of Phase-Locked Loop(PLL), the external system clock with high frequency accuracy but poor phase noise is converted into an internal clock signal with high frequency accuracy and low phase noise simultaneously. The internal clock source is coherent with the external source by the PLL as well. The effect of the PLL loop bandwidth on the phase noise of the output signal is analyzed emphatically through both simulations and measurements. Test results show that, at 100 Hz of loop bandwidth, the phase noise of the PLL output signal basically equals to that of the internal oscillator at 1 kHz away from the carrier. While at 500 Hz of loop bandwidth, the phase noise of the PLL output signal is decreased by 8 dB at the same place, compared to the internal oscillator phase noise, due to being affected by the loop filter. The phase noise of the proposed 100 MHz clock source is better than -147 dBc/Hz@1 kHz, which is improved by 12 dB than that of the external reference clock signal，and the frequency accuracy can reach up to 1×10^-9.