设计了一种带隔直电容的交流耦合CTIA像元电路与数字相关双采样(DCDS)结构的CMOS图像传感器系统。在传统的CTIA像元电路中增加隔直电容, 通过控制光电二极管的偏压, 达到减小光电二极管暗电流的目的; 同时采用片外数字CDS结构, 通过在片外实现复位信号与像元积分信号的量化结果在数字域的减法, 可以减小图像传感器像元的复位噪声和固定图案噪声(FPN)。基于0.35 μm标准CMOS工艺对此CMOS图像传感器进行流片, 像元阵列为256×256, 像元尺寸为16 μm×16 μm。测试结果表明交流耦合CTIA像元电路可以将光电二极管的偏压控制在零偏点附近, 此时其暗电流最小; 采用了数字CDS结构后, 图像传感器像元的时域噪声及固定图案噪声均有不同程度降低。

A CMOS image sensor with coupling capacitor based AC-coupled CTIA and digital CDS was proposed. By adding a coupling capacitor to the conventional CTIA circuit, the dark current of the photodiode was reduced via controlling the bias voltage of the photodiode; Meanwhile, an off-chip digital CDS was adopted to reduce the reset noise of the pixel and the FPN by realizing the subtraction algorithm between the reset signal and pixel signal after A/D conversion off-chip. This CMOS image sensor was implemented in the 0.35 μm standard CMOS technology. The pixel array was 256×256, and the pixel size was 16 μm×16 μm. The experimental results show that the dark current can be minimized by reducing the bias of the photodiode nearby zero. The temporal noise and FPN are obviously reduced after adopting the off-chip digital CDS.