针对目前缩放插值算法中硬件实现比较复杂、资源消耗多、运算处理时间长、实时性较差等缺陷, 介绍了一种基于图像的双线性插值缩放算法的设计方法, 同时对算法中的浮点运算进行优化, 节省了电路的硬件开销。最终搭建了FPGA验证平台, 实现了图像的任意比缩放, 证明了设计的可行性, 达到了实验预期的目的。

The current zoom interpolation algorithm has the problems of hardware implementation complexity, high resource consumption, long operation time and poor realtime. A design of bilinear interpolation algorithm based on image zooming was introduced, and the algorithm in the floating-point operation was optimized, saving the hardware expenses. In the end, FPGA platform was built and the feasibility of the design was verified, achieving the expected purpose.