矩阵运算广泛应用于实时性要求的各类电路中, 其中矩阵求逆运算最难以实现。基于现场可编程门阵列 (FPGA)实现矩阵求逆能够充分发挥硬件的速度与并行性优势, 加速求逆运算过程。基于改进的脉动阵列的计算架构, 采用一种约化因子求逆的优化算法, 将任意一个 n×n阶上三角矩阵转换成对角线为 1的上三角矩阵, 使得除法运算与乘加运算分离开来, 大大简化矩阵求逆运算过程。以一个 4×4阶上三角矩阵求逆为例, 在 Xilinx ISE平台下, 采用 Virtex5 FPGA完成算法实现与功能验证, 在 14个周期内, 使用了 2个除法器, 3个乘法器与 4个加法器实现整个矩阵求逆运算。相比于经典的脉动阵列架构, 仅占用近一半资源的同时, 性能提升了 26.43%; 相比于集成更多处理单元 (PE)的脉动阵列实现方式, 在性能近乎不变的情况下, 耗费的资源缩减到 1/4, 大幅度提升了资源利用率。

It’s practically complicate to implement the matrix inversion which is widely used in all kinds of real-time circuit calculation. Taking Field Programmable Gate Arrays(FPGA) to implement the operation is able to take advantages of the hardware’s speed and parallelism to accelerate the matrix inversion. Based on improved systolic architecture, a simplification factor algorithm is proposed, in which any n×n upper-matrix is transferred into an upper-matrix whose diagonal value is 1 to split dividing processor with multiplying and adding processor to greatly simplify the matrix inversion. Taking a 4×4 upper-matrix as an example, the algorithm is implemented and executed the functional verification adopting Virtex5 device in Xilinx ISE and utilizing 2 dividers, 3 multipliers and 4 adders in 14 cycles to accomplish all matrix inversion. Compared with the classical systolic architecture, resources are just occupied nearly half, while performance gets improved by 26.43%. Compared with systolic architecture integrated more Processing Elements(PE), the performance does not change and the resources reduce to 1/4, which greatly improves the resources utilization.