随着信号处理算法的发展, 人们对航天用现场可编程门阵列(Field Programmable Gate Array, FPGA)提出了算法可更新的需求。而传统的固定算法模式已经无法满足要求, 所以星上FPGA在轨可重构设计成为了解决这一问题的关键。提出了一种基于星地链路的FPGA在轨可重构设计方案。通过星地链路上载配置数据并将其存入电可擦除只读存储器(Electrically Erasable Programmable Read Only Memory, EEPROM)内, 然后利用反熔丝器件对FPGA进行大规模算法重配置操作。这项设计方案已经通过了相关验证, 同时也提升了星载FPGA的灵活性。

With the development of signal processing algorithms, the algorithm updatable requirement is put forward for the Field Programmable Gate Array (FPGA) used in the field of space. Since traditional fixed algorithm models could not meet this requirement, the in-orbit reconfigurable design of FPGAs onboard satellites becomes the key to solve the problem. A FPGA reconfigurable design scheme based on the satellite-to-ground link is proposed. In the scheme, the configuration data are uploaded through the satellite-to-ground link and are stored in the Electrically Erasable Programmable read only memory (EEPROM). Then, an antifuse device is used to implement large scale algorithm reconfiguration on the FPGA. This design scheme is verified and the flexibility of the space-borne FPGAs is improved.