隔离槽的制作是实现阵列芯片单元独立的有效方法。本文采用感应耦合等离子体干法刻蚀(ICP)和具有高刻蚀比的SiO2与光刻胶混合掩膜在GaN基微尺寸LED上制备了3种深度的隔离槽和6种不同的芯片尺寸结构。通过电致发光(EL)和电容计表征不同刻蚀深度对LED芯片电学性能和电容大小的影响。实验结果表明, 小尺寸的芯片有着更高的电流承受密度和更小的电容值, 隔离槽刻蚀深度的增加能降低电容和电阻, 从而使RC时间常数得到降低。有源层直径为 120 μm的芯片从仅有Mesa刻蚀到完全刻蚀到蓝宝石衬底, 其RC调制带宽从155 MHz增大到176 MHz。减小芯片尺寸和完全刻蚀到蓝宝石衬底能有效减小芯片RC常数。这些工作将有助于GaN基LED的未来设计和制造, 以提高高频可见光通信的调制带宽和光功率。

The fabrication of the isolation trough is an effective way to realize independence of the array chip unit. In this paper, four kinds of isolation depth and six different chip sizes were fabricated on GaN-based LED arrays using inductively coupled plasma dry etching(ICP) with high etching ratio hybrid-mask SiO2 and photoresist. The effect of different etching sizes and depths on the electrical performance of LED array chip was characterized by electroluminescence(EL) and capacitance tester. The experimental results show that the smaller chip has a higher endured current density and smaller capacitance. With the increase of the etching depth, both the resistance and capacitance decrease, which reduces the RC time constant. The RC bandwidth of the samples with 120 μm Mesa increases from 155 MHz to 176 MHz when the etch depth is from Mesa etch only to completely etch to the sapphire substrate. Reducing the chip size and completely etching to the sapphire substrate can effectively reduce the chip RC time constant. These efforts will facilitate the future design and manufacture of GaN-based LEDs to improve the modulation bandwidth of high-frequency visible light communications.