单粒子瞬态脉冲宽度是评价电子系统软错误率的重要参数之一。针对0.13 μm、部分耗尽型绝缘体上硅(PDSOI)工艺下的反相器链，解析地计算了反相器中产生的单粒子瞬态脉冲宽度，仿真了产生的单粒子瞬态脉冲在反相器链中传播时的临界脉冲宽度和传输率随级数变化情况。仿真结果表明，单粒子瞬态脉冲宽度的大小在几十皮秒到几百皮秒之间，反相器链的级数对临界脉冲宽度和传输率影响较大。最后仿真得到在输入单粒子瞬态脉冲宽度较小时，建立保持时间与输入脉冲宽度有关。该结果有利于电气掩蔽建模和锁存掩蔽建模准确性的提高。

The width of Single-Event Transient(SET) pulse is one of the most important parameters for evaluating soft-error rate in electronic systems. Analytical calculation is performed in 0.13 μm Partially Depleted Silicon On Insulator(PDSOI) Complementary Metal Oxide Semiconductor(CMOS) logic. Simulation in inverter chain is carried out to study the variation of critical pulse width and transmission rate. Results reveal that SET pulse width changes from dozens of picosecond to hundreds of picosecond in duration; meanwhile, the stage of inverter chain has a great influence on critical pulse width and transmission rate. Finally，derived by simulation of D Flip-Flop(DFF)，the set-up time and hold time are related to the input pulse width when pulse width is short. The results are helpful for improving the accuracy of electrical masking model and latch masking model.