设计了一种片上集成的高精确度、低功耗、无片外电容的低压差线性稳压器( LDO)。采用一种新型高精确度、带隙基准电压源电路降低输出电压温漂系数；采用零功耗启动电路和支路较少的摆率增强模块降低功耗，该电路采用 CSMC 0.5 μm CMOS工艺。经过 Cadence Spectre仿真验证，输出电压为 3.3 V，在3.5~5.5 V范围内变化时，线性调整率小于 0.3 mV/V，负载调整率小于 0.09 mV/mA，输出电压在 -40~+150 ℃范围内温漂系数达 10 ppm/℃，整个 LDO消耗17.7 μA的电流。

A full on chip high precision low power capacitor-less Low Dropout Regulator(LDO) is presented. The circuit realizes high precision by using a high-order curvature compensated bandgap circuit. The power consumption is effectively decreased by using a zero power start-up circuit. In addition, 4 transistors are utilized to enhance slew rate which is good for low power consumption. The circuit was simulated in CSMC 0.5 μm CMOS process. By simulation with Spectre, the circuit achieves an output voltage of 3.3 V, a line regulation less than 0.3 mV/V, a load regulation less than 0.09 mV/mA, a temperature coefficient of 10 ppm/℃ in the temperature range from -40 ℃ to 150 ℃. The total LDO circuit consumes 17.7 μA.计.