可编程逻辑块是现场可编程门阵列 (FPGA)的核心组成部分 (主要由查找表 (LUT)和寄存器构成 )，它的内部结构设计一直是研究的重要方向。可拆分逻辑结构给电路实现带来了灵活性。本文以 6-LUT作为研究对象，从拆分粒度的角度出发，研究不同的可拆分因子 (N=1,2,3,4)对电路性能带来的影响。仿真实验基于开源的 FPGA CAD工具(ABC和 VPR)和 VPR测试电路集，实验结果表明： a) 不同可拆分因子对电路关键路径延时影响不大； b) 可拆分因子为 2时，电路使用资源的面积和面积 -延时积均最小，呈现更好的性能。

Programmable logic, which mainly consists of LUTs and registers, is a central part of Field Programmable Gate Array(FPGA) architecture. Exploring the structure of the programmable logic is important in FPGA’s research. Fracturable logic can bring flexibility during circuit implementation. In this paper, the influences of fracturable factor on the performance of circuit are studied from the point of view of fracturable logic based on 6-LUT. Simulation experiment is based on open-source FPGA CAD tools－ABC and VPR, and the circuits are from VPR benchmarks. The performance is evaluated from three aspects: area, delay and area-delay product. The experiment results show that: a) the fracturable factor does not make much influence on critical path delay; b) discussing from the aspects of area and area-delay product, the circuit will perform better when assigning the value of fracturable factor to 2.