为实现数字BPM时钟系统的锁相, 设计了一种基于锁相环同步原理的低抖动、低相位噪声的时钟同步系统。根据锁相环电路工作原理, 对数字BPM时钟同步系统的硬件及固件程序进行了设计, 实现了外部输入时钟信号与系统内部产生的主工作时钟信号的锁相, 并且时钟信号输出的频率及相位均可调整以满足后端ADC采样的要求。测试结果表明, 设计可以完成对一定频率范围内变化的外部输入时钟信号的锁相, 输出时钟信号抖动满足束流实验要求, 为数字BPM后续算法研究提供了基础。

In order to realize the phase locking of the digital beam position monitor (BPM) clock system, a clock synchronization system with low jitter and low phase noise is designed based on the principle of PLL synchronization. According to the working principle of the PLL circuit, the hardware and firmware are designed for the digital BPM clock synchronization system, the phase locking of the external input clock signal and the systems internal main work clock signal is realized, the output frequency and phase of the clock signal can be adjusted to meet the ADC sampling requirements in the back-end. The test results show that the design can meet the phase locking for the external clock signal which changes in a certain frequency range and the output clock signal jitter satisfies the requirement of beam experiments. Meanwhile, this study provides a basis for the subsequent research of digital BPM.