随着CMOS图像传感器(CIS)向片上系统化、高度集成化方向发展, 片内锁相环(PLL)成为系统不可或缺的片上时钟模块, 而高速高集成的CIS对PLL的高频时钟输出能力提出了新的挑战。介绍了一种基于0.13μm CIS工艺设计的电荷泵PLL模块, 该模块工作于1.5V电压, 利于控制功耗; 具备压控振荡器(VCO)电流自偏置和自校准技术, 可提供最高频率为480MHz的输出信号和更好的噪声性能; 多种输入输出倍频可选功能使其能够满足多样化的片上时钟生成需求, 提高可复用性。仿真结果表明, 当实现12倍频且输出频率为480MHz时, 该PLL模块输出信号的均方根周期抖动为837fs, 功耗为2.817mW, 满足高速CIS对时钟速度的需求, 同时保证了输出时钟的低噪声和模块本身的低功耗。

With the development trend of system-on-chip and high integration of CMOS image sensor(CIS), phase-locked loop (PLL) becomes an essential on-chip clock module for CIS. While highly integrated and high-speed CIS put new challenges to the high-frequency output capability of PLL. A charge-pump PLL module based on a 0.13μm CIS process is presented. It works under 1.5V supply voltage for power consumption control, VCO self-biasing and self-calibration techniques are good for the output frequency of up to 480MHz and better noise performance, various frequency multiplier sets satisfies diversified clock generation applications and improves reusability. Simulation results show that the RMS period jitter of output signal is 837fs and the power consumption is 2.817mW when the PLL module is set to output signal with the frequency of 480MHz and 12 multiplier. It satisfies the frequency requirement of high-speed CIS clock, and also ensures low output noise and low power consumption of the module itself.