为减小现场可编程门阵列(FPGA)关键路径的延时误差, 提出一种基于时延配置表的静态时序分析算法。算法建立了一种基于单元延时与互连线延时配置表的时延模型。该模型考虑了工艺角变化对延时参数的影响, 同时在时序分析过程中, 通过分析路径始节点与终节点的时钟关系, 实现了复杂多时钟域下的路径搜索与延时计算。实验结果表明, 与公认的基于查找表的项目评估技术(PERT)算法和VTR算法相比, 关键路径延时的相对误差平均减少了8.58%和6.32%, 而运行时间平均仅增加了19.96%和9.59%。

A static timing analysis algorithm is proposed, which applies the delay collocation table, to reduce the relative error of critical path delay in Field Programmable Gate Array(FPGA). Based on the collocation table model of the logic element delay and interconnect delay, the algorithm takes into account the process corner variation's effect on delay parameters. In timing analysis phase, by computing the clock relationship between source node and sink node, path searching and delay calculating in multi-clock domains are achieved. Experimental results demonstrate that the relative error of critical path delay is reduced by 8.58% and 6.32% respectively on average when compared with the Program Evaluation and Review Technique(PERT) and the VTR algorithm, while the run time is only increased by 19.96% and 9.59% respectively on average.