针对低等级器件抗辐射能力较差的特点，需开展应用加固以满足宇航应用，对一款Flash型现场可编程门阵列(FPGA)开展抗单粒子翻转(SEU)加固设计，并利用地面模拟试验进行加固效果验证，结果表明器件加固后块随机存储器(BRAM)区翻转截面下降近2个数量级，寄存器单粒子翻转截面下降约75%，验证了加固措施的有效性。结合典型轨道环境，计算了器件在轨翻转率，BRAM区翻转率下降4~5个量级，寄存器翻转率下降2~3个量级，可为在轨应用提供指导。

For the feature that the anti-radiation ability of Commercial Off The Shelf(COTS) devices is poor, it must be hardened for aero application. Then Single Event Upset(SEU) hardened design is done for a Flash Field-Programmable Gate Array(FPGA), and the ground ions accelerated testing is performed to verify the hardened design measures. The test result shows that the upset section of hardened Block RAM(BRAM) module reduces nearly 2 orders of magnitude, and the upset section of hardened register module reduces 75%. It verifies the validity of the hardened measures. According to the orbits environment, the SEU rate is calculated, the SEU rate of hardened BRAM module reduces 4–5 orders of magnitude, and the SEU rate of hardened register module reduces 2–3 orders of magnitude. It provides guidance for on-orbit applications.