设计了一种单时钟域内低级展开、高级折叠的多级离散小波变换架构;采用横向三输入扫描方式,基于9/7离散小波变换提升算法,设计第1级离散小波变换模块;根据第2级离散小波变换的时钟周期与有效输入数据之比,设计半折叠的第2级离散小波变换模块;将第3级及更高级的离散小波变换的架构折叠到第2级离散小波变换架构上,从而降低了硬件资源的消耗。结果表明:对于大小为512 pixel×512 pixel的经3级离散小波变换处理的输入图像,所提架构的硬件效率比其他现有架构提高了57.1%以上。

A lower-level unfolded and higher-level folded multi-level discrete wavelet transform architecture in single-clock domain is proposed. A three-input line-based scanning method is adopted. The first-level discrete wavelet transform is designed based on the 9/7 discrete wavelet transform lifting scheme. The partially folded second-level discrete wavelet transform is constructed according to the ratio of clock cycles to valid input data. The third-level and higher-level discrete wavelet transform architectures are folded into the second-level discrete wavelet transform architecture to reduce the consumption of hardware resources. The results show that for the input image with size of 512 pixel×512 pixel processed by the three-level discrete wavelet transform, the hardware efficiency of the proposed architecture increases over 57.1% compared with the existing architectures.