面向模拟总线接收器应用，设计实现了一款CMOS增益可编程低噪声放大器(LNA)。内置高/中/低增益3个信号放大通路，以满足不同信号幅度情况下的模拟总线接收时的噪声、线性度与输入阻抗等性能需求。提出电容补偿漏电流方法提高高增益信号通路放大器的输入阻抗，同时采用带宽拓展负载方法降低信号相移，解决放大器相移造成电流补偿能力降低的问题。中/低增益信号通路放大器采用差分多门控晶体管(DMGTR)和负反馈技术提高放大器线性度。放大器基于0.18 μm CMOS工艺设计，在1~33 MHz频段，增益范围为-14.3~25 dB，输入阻抗大于2.4 kΩ，输入三阶交调点(IIP3)为-1.6 dBm(最大为20.7 dBm)，在25 dB增益下等效输入噪声为~ ，1.8 V电源电压下工作电流为6.5 mA。

A CMOS programmable gain Low Noise Amplifier(LNA) is implemented for analog bus receiver applications. There are high/medium/low gain channels, which are applied to meet noise, linearity and input impedance and other performance requirements in analog bus reception in condition of different input signal amplitude. The technique is adopted to compensate the input leakage current of LNA via a capacitor, which yields a real-time high-input impedance. The bandwidth-extension loads is adopted to reduce the phase shift, which solves the current compensating faulty because of the phase shift. An improvement of linearity in medium/low gain channels is achieved by applying Differential Multiple Gated Transistor(DMGTR) and negative feedback technique. The amplifier is designed using 0.18 μm CMOS technology. The simulation result exhibits a gain of -14.3 dB to -25 dB, an input impedance higher than 2.4 kΩ, an -1.6 dBm Input Third-order Intercept Point(IIP3)(maximum 20.7 dBm), an input-referred noise voltage of - in the 25 dB gain mode and an power consumption of 6.5 mA at 1.8 V at frequencies from 1 MHz to 33 MHz.