半导体光电, 2018, 39 (6): 806, 网络出版: 2019-01-10  

边沿触发器亚稳态现象的实验观测

Experimental Observation of Metastable Phenomena of Edge Triggered Flip Flops
作者单位
1 中国空间技术研究院 通信卫星事业部, 北京 100094
2 四川大学 电子信息学院, 成都 610064
摘要
在跨时钟域数据传输中, 常因违反触发器的建立时间和保持时间要求而产生亚稳态现象, 导致数据误码。为对亚稳态发生过程进行直观观测, 利用所搭建的亚稳态观测平台, 在建立时间区域对TTL维持阻塞型集成边沿触发器74LS74芯片和CMOS传输门型集成边沿触发器74HC74芯片分别进行了误码测试。测试结果表明, 两芯片性能接近, 在建立时间0.9~1.6ns区间存在0%~100%误码过渡带, 能观测亚稳态过程的直观波形。测试过程中, 发现触发器输入电平上跳变时, 误码率在以上区间存在稳定的单调变化曲线。当触发器输入电平下跳变时, 误码率会从0%瞬变到100%, 实验未观测到过渡带。输入下跳变时, 当延迟参量单向递增或递减时, 瞬变区域不一样, 存在回差现象。
Abstract
In cross-clock data transmission, metastable phenomena often occur due to violation of the setup time and hold time of flip-flops, resulting in bit error. In order to observe the metastable process directly, it uses the metastable observation platform to test the bit error of TTL block holding integrated edge flip-flop 74LS74 chip and CMOS transmission gate integrated edge flip-flop 74HC74 chip in setup time domain. Test results show that the performance of the two chips is close, and there is a 0%~100% BER transition band in the setup time of 0.9~1.6ns, in which the visual waveform of metastable process can be observed. It is found that there is a stable monotonic variation curve of BER in the above range when the input level of trigger jumps up. When the input level of the flip-flop jumps down, the BER changes from 0% to 100% instantaneously, and the transition zone cannot be observed. When the input jumps down and the delay parameter increases or decreases in one direction, the transient region will be different and presents a backlash phenomenon.
参考文献

[1] Horstmann J U, Eichel H W, Coates R L. Metastability behavior of CMOS ASIC flip-flops in theory and test[J]. IEEE J. of Solid-State Circuits, 1989, 24(1): 146-157.

[2] Kleeman L, Cantoni A. Metastable behavior in digital systems[J]. IEEE Design & Test of Computers, 1987, 4(6): 4-19.

[3] 李 立, 龙泳涛, 曾钢燕, 等. 可编程逻辑器件设计中的亚稳态问题及解决方案[J]. 湘潭大学自然科学学报, 2009, 31(1): 125-129.

    Li Li, Long Yongtao, Zeng Gangyan, et al. The metastability and solutions method in CPLD design[J]. Natural Science J. of Xiangtan University, 2009, 31(1): 125-129.

[4] 黄隶凡, 郑学仁. FPGA设计中的亚稳态研究[J]. 微电子学, 2011, 41(2): 265-268.

    Huang Lifan, Zheng Xueren. Study on metastability in FPGAdesign[J]. Microelectronics, 2011, 41(2): 265-268.

[5] Kleeman L, Cantoni A. Metastable behavior in digital systems[J]. IEEE Design & Test of Computers, 1987, 4(6): 4-19.

[6] Rosenberger F,Chaney T J. Flip-flop resolving time test circuit[J]. IEEE J. of Solid-State Circuits, 1982, 17(4): 731-738.

[7] Kinniment D, Heron K, Russell G. Measuring deep metastability[C]// IEEE Inter. Symp. Asynchronous Circuits and Systems of Computer Society, 2006: 2.

[8] Fairchild Semiconductor. 74LS74 Datasheet[DB/OL]. www.fairchildsemi.com

[9] Fairchild Semiconductor. 74HC74 Datasheet[DB/OL].www.fairchildsemi.com

侯凤妹, 李长安, 赵刚. 边沿触发器亚稳态现象的实验观测[J]. 半导体光电, 2018, 39(6): 806. HOU Fengmei, LEE Changan, ZHAO Gang. Experimental Observation of Metastable Phenomena of Edge Triggered Flip Flops[J]. Semiconductor Optoelectronics, 2018, 39(6): 806.

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