FIR基于 FPGA的高并行度 DA结构

林跃杉; 林郁; 尹韬; 黄志洪; 杨海钢

doi:doi:10.11805/tkyda201801.0170

太赫兹科学与电子信息学报, 2018, 16 (1): 170, 网络出版: 2018-07-24

FIR基于 FPGA的高并行度 DA结构

FPGA based high parallelism DA architecture for FIR

论文大纲

林跃杉 ^1,2,*林郁 ¹尹韬 ¹黄志洪 ¹杨海钢 ^1,2

作者单位

¹ 中国科学院电子学研究所，北京 100190

² 中国科学院大学，北京 100049

摘要

有限长单位冲击响应滤波器 (FIR)是合成孔径雷达 (SAR)系统的重要组成部分。为综合考虑资源与性能对系统的影响，基于现场可编程门阵列 (FPGA)设计实现了位宽、阶数可配置的 SAR雷达信号处理 FIR系统，首次完成了合理范围内的只读存储器 (ROM)地址位宽和所有输入并行度设置下的分布式算法 (DA)结构对比实验，并对不同结构实现下的系统性能资源比进行了全面分析和比较，得到了最优化高并行度 DA结构。实验结果表明在 ROM地址位宽为 4或 5时性能资源比最好；性能资源比随输入并行度的提高而提高，当输入并行度为输入数据位宽时，性能资源比提高 24%至 117%。对比传统的全串行结构、全并行结构和 DA结构，经 ROM地址位宽和输入并行度优化后的 DA结构的性能资源比分别提高了 3 110%,76%和 86%。

Abstract

Finite Impulse Response(FIR) is an important component in Synthetic Aperture Radar (SAR) signal processing system. Considering both of the resource and performance impact for system, based on FPGA(Field Programmable Gate Array), a SAR signal processing FIR is designed with width and order of filter configurable. By comparing DA(Distributed Arithmetic) architectures with the meaningful address width of ROM(Read Only Memory) and different input parallelism, and analyzing the throughput-resource ratio of different architectures, the best high parallelism DA architecture is obtained. Experimental results show that throughput-resource ratio is best when address width of ROM is 4 or 5; and the throughput-resource ratio increases when input parallelism increases, and when input parallelism equals to input data width, throughput-resource ratio is improved by 24%-117%. Compared to traditional fully parallel architecture, fully serial architecture and DA architecture, optimized DA architecture can improve the throughput-resource ratio by 3 110%, 76% and 86%, respectively.

参考文献

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林跃杉, 林郁, 尹韬, 黄志洪, 杨海钢. FIR基于 FPGA的高并行度 DA结构[J]. 太赫兹科学与电子信息学报, 2018, 16(1): 170. LIN Yueshan, LIN Yu, YIN Tao, HUANG Zhihong, YANG Haigang. FPGA based high parallelism DA architecture for FIR[J]. Journal of terahertz science and electronic information technology, 2018, 16(1): 170.

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